Bus Blaster is meant to be compatible with jtag key, so we can use jtag key config as template and modify as necessary. openocd_busblaster.cfg
interface ftdi
ftdi_device_desc "Dual RS232-HS"
ftdi_vid_pid 0x0403 0x6010
ftdi_layout_init 0x0c08 0x0f1b
ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
Right now there is no existing .cfg file for RK3368, so we need to create one on our own, using the detected information. so create a temporary openocd_detect.cfg first with such content
transport select jtag
# we need to enable srst even though we don't connect it
reset_config trst_and_srst
adapter_khz 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rk3368
}
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}
jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
set _TARGETNAME $_CHIPNAME.cpu
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap
And with the above 2 files, we can run openocd with telnet:
openocd -f '/home/julian/geekbox/mmallow/openocd_busblaster.cfg' -f '/home/julian/geekbox/mmallow/openocd_detect.cfg'
Open On-Chip Debugger 0.10.0+dev-00921-g263deb38 (2019-07-28-21:16)
Licensed under GNU GPL v2
For bug reports, read
http://openocd.org/doc/doxygen/bugs.html
Info : Listening on port 6666 for tcl connections
Info : Listening on port 4444 for telnet connections
Info : clock speed 8 kHz
Info : JTAG tap: rk3368.dap tap/device found: 0x5ba00477 (mfg: 0x23b (ARM Ltd.), part: 0xba00, ver: 0x5)
Info : Listening on port 3333 for gdb connections
Info : accepting 'telnet' connection on tcp/4444
And in another window, start a telnet session to type commands
telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> dap info 1
AP ID register 0x44770002
Type is MEM-AP APB
MEM-AP BASE 0x80000003
Valid ROM table present
Component base address 0x80000000
Peripheral ID 0x04000bb4a9
Designer is 0x4bb, ARM Ltd.
Part is 0x4a9, Cortex-A9 ROM (ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
ROMTABLE[0x0] = 0x1003
Component base address 0x80001000
Peripheral ID 0x04002bb908
Designer is 0x4bb, ARM Ltd.
Part is 0x908, CoreSight CSTF (Trace Funnel)
Component class is 0x9, CoreSight component
Type is 0x12, Trace Link, Funnel, router
ROMTABLE[0x4] = 0x3003
Component base address 0x80003000
Peripheral ID 0x04004bb906
Designer is 0x4bb, ARM Ltd.
Part is 0x906, CoreSight CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
ROMTABLE[0x8] = 0x4003
Component base address 0x80004000
Peripheral ID 0x04001bb101
Designer is 0x4bb, ARM Ltd.
Part is 0x101, Unrecognized
Component class is 0xf, PrimeCell or System component
ROMTABLE[0xc] = 0x5003
Component base address 0x80005000
Peripheral ID 0x04004bb912
Designer is 0x4bb, ARM Ltd.
Part is 0x912, CoreSight TPIU (Trace Port Interface Unit)
Component class is 0x9, CoreSight component
Type is 0x11, Trace Sink, Port
ROMTABLE[0x10] = 0x20003
Component base address 0x80020000
Peripheral ID 0x04003bb4a3
Designer is 0x4bb, ARM Ltd.
Part is 0x4a3, Cortex-A53 ROM (v7 Memory Map ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
[L01] ROMTABLE[0x0] = 0x10003
Component base address 0x80030000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x4] = 0x11003
Component base address 0x80031000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x8] = 0x12003
Component base address 0x80032000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0xc] = 0x13003
Component base address 0x80033000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x10] = 0x14003
Component base address 0x80034000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x14] = 0x15003
Component base address 0x80035000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x18] = 0x16003
Component base address 0x80036000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x1c] = 0x17003
Component base address 0x80037000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x20] = 0x18003
Component base address 0x80038000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x24] = 0x19003
Component base address 0x80039000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x28] = 0x1a003
Component base address 0x8003a000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x2c] = 0x1b003
Component base address 0x8003b000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x30] = 0x1c003
Component base address 0x8003c000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x34] = 0x1d003
Component base address 0x8003d000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x38] = 0x1e003
Component base address 0x8003e000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x3c] = 0x1f003
Component base address 0x8003f000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x40] = 0x0
[L01] End of ROM table
ROMTABLE[0x14] = 0x40003
Component base address 0x80040000
Peripheral ID 0x04003bb4a3
Designer is 0x4bb, ARM Ltd.
Part is 0x4a3, Cortex-A53 ROM (v7 Memory Map ROM Table)
Component class is 0x1, ROM table
MEMTYPE system memory not present: dedicated debug bus
[L01] ROMTABLE[0x0] = 0x10003
Component base address 0x80050000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x4] = 0x11003
Component base address 0x80051000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x8] = 0x12003
Component base address 0x80052000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0xc] = 0x13003
Component base address 0x80053000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x10] = 0x14003
Component base address 0x80054000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x14] = 0x15003
Component base address 0x80055000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x18] = 0x16003
Component base address 0x80056000
Peripheral ID 0x04003bbd03
Designer is 0x4bb, ARM Ltd.
Part is 0xd03, Cortex-A53 Debug (Debug Unit)
Component class is 0x9, CoreSight component
Type is 0x15, Debug Logic, Processor
[L01] ROMTABLE[0x1c] = 0x17003
Component base address 0x80057000
Peripheral ID 0x04003bb9d3
Designer is 0x4bb, ARM Ltd.
Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
Component class is 0x9, CoreSight component
Type is 0x16, Performance Monitor, Processor
[L01] ROMTABLE[0x20] = 0x18003
Component base address 0x80058000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x24] = 0x19003
Component base address 0x80059000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x28] = 0x1a003
Component base address 0x8005a000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x2c] = 0x1b003
Component base address 0x8005b000
Peripheral ID 0x04003bb9a8
Designer is 0x4bb, ARM Ltd.
Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
Component class is 0x9, CoreSight component
Type is 0x14, Debug Control, Trigger Matrix
[L01] ROMTABLE[0x30] = 0x1c003
Component base address 0x8005c000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x34] = 0x1d003
Component base address 0x8005d000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x38] = 0x1e003
Component base address 0x8005e000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x3c] = 0x1f003
Component base address 0x8005f000
Peripheral ID 0x04003bb95d
Designer is 0x4bb, ARM Ltd.
Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
Component class is 0x9, CoreSight component
Type is 0x13, Trace Source, Processor
[L01] ROMTABLE[0x40] = 0x0
[L01] End of ROM table
ROMTABLE[0x18] = 0x0
End of ROM table
With the detected ROM table information, now we can write a .cfg specifically for Geekbox RK3368 openocd_geekbox.cfg:
transport select jtag
# we need to enable srst even though we don't connect it
reset_config trst_and_srst
adapter_khz 8
#jtag_ntrst_delay 500
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME rk3368
}
#
# Main DAP
#
if { [info exists DAP_TAPID] } {
set _DAP_TAPID $DAP_TAPID
} else {
set _DAP_TAPID 0x5ba00477
}
#TSAI: I don't know what SAP is, and it's giving error
#if { [info exists SAP_TAPID] } {
# set _SAP_TAPID $SAP_TAPID
#} else {
# set _SAP_TAPID 0x06b2001d
#}
jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
#jtag newtap $_CHIPNAME sap -irlen 8 -expected-id $_SAP_TAPID
set _TARGETNAME $_CHIPNAME.cpu
set _TARGETNAME_1 $_CHIPNAME.cpu1
set _TARGETNAME_2 $_CHIPNAME.cpu2
set _TARGETNAME_3 $_CHIPNAME.cpu3
set _TARGETNAME_4 $_CHIPNAME.cpu4
set _TARGETNAME_5 $_CHIPNAME.cpu5
set _TARGETNAME_6 $_CHIPNAME.cpu6
set _TARGETNAME_7 $_CHIPNAME.cpu7
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
cti create $_CHIPNAME.cti -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80038000
cti create $_CHIPNAME.cti1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80039000
cti create $_CHIPNAME.cti2 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x8003A000
cti create $_CHIPNAME.cti3 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x8003B000
cti create $_CHIPNAME.cti4 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80058000
cti create $_CHIPNAME.cti5 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x80059000
cti create $_CHIPNAME.cti6 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x8005A000
cti create $_CHIPNAME.cti7 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0x8005B000
target create $_TARGETNAME aarch64 -dap $_CHIPNAME.dap -coreid 0 -dbgbase 0x80030000 -cti $_CHIPNAME.cti
target create $_TARGETNAME_1 aarch64 -dap $_CHIPNAME.dap -coreid 1 -dbgbase 0x80032000 -cti $_CHIPNAME.cti1
target create $_TARGETNAME_2 aarch64 -dap $_CHIPNAME.dap -coreid 2 -dbgbase 0x80034000 -cti $_CHIPNAME.cti2
target create $_TARGETNAME_3 aarch64 -dap $_CHIPNAME.dap -coreid 3 -dbgbase 0x80036000 -cti $_CHIPNAME.cti3
target create $_TARGETNAME_4 aarch64 -dap $_CHIPNAME.dap -coreid 4 -dbgbase 0x80050000 -cti $_CHIPNAME.cti4
target create $_TARGETNAME_5 aarch64 -dap $_CHIPNAME.dap -coreid 5 -dbgbase 0x80052000 -cti $_CHIPNAME.cti5
target create $_TARGETNAME_6 aarch64 -dap $_CHIPNAME.dap -coreid 6 -dbgbase 0x80054000 -cti $_CHIPNAME.cti6
target create $_TARGETNAME_7 aarch64 -dap $_CHIPNAME.dap -coreid 7 -dbgbase 0x80056000 -cti $_CHIPNAME.cti7
$_TARGETNAME configure -event reset-assert-post "aarch64 dbginit"
$_TARGETNAME configure -event gdb-attach { halt }
My Notes 